1. Field of the Invention
The present invention generally relates to testing devices, and more particularly to a circuit that operates in conjunction with a scan buffer for evaluating timing characteristics of electrical signals in an integrated circuit.
2. Discussion of the Related Art
A variety of automatic test equipment (ATE) have long been known for testing electronic circuits, devices, and other semiconductor and electronic products. Generally, automatic test equipment are divided into two broad categories, analog testers and digital testers. As the names imply, analog testers are generally designed for testing analog circuit devices, while digital testers are designed for testing digital circuit devices. ATE are programmably controlled to be adapted or configured to test a variety of devices in a variety of ways. This is achieved by programming ATE inputs to inject a certain signal (or signal transition) and by programming ATE outputs to compare a value to a certain pin or signal line on a DUT.
An integrated circuit tester includes a set of modules or "nodes", wherein one node is associated with each terminal of a device under test (DUT). When the DUT is an integrated circuit chip (IC) chip, then one node may be associated with each pin of the IC chip. A test is organized into a set of successive time segments ("test cycles"). During any given test cycle, each node can either transmit a test signal to the pin, sample a DUT output signal at the associated pin, or do neither. Each node includes its own memory for storing a sequence of these transmit or sample commands ("test vectors").
As is known by those skilled in the art, a test generator is independent and distinct from a tester. A test generator uses a model of a device to formulate a set of test vectors that will efficiently test for and detect faults on the tested device. Whereas, a tester is a device disposed downstream of the test generator. It utilizes the set of test vectors generated by the test generator in order to test the actual device.
A test vector or test pattern, as generated by a test generator, is a string of n logic values (0, 1, or don't care-X) that are applied to the n corresponding primary inputs (PIs) of a circuit at the same time frame. A test sequence is a series of test vectors applied to a sequential circuit in a specific order to detect a target fault. The first vector in the test sequence assumes the circuit to be in a completely unknown state. A test set is an unordered set of test sequences.
Using the principals describe above, and as is known in the art, testing may be carried out on an integrated circuit to completely test its functionality, both with respect to combinational logic portions and sequential logic portions. Although this ability to test circuitry that is deeply embedded within an integrated circuit has vastly improved the design and debug of complex integrated circuit devices, further improvements are desired.
Specifically, one area where further improvements are desired relates to the area of timing evaluation. In connection with the design and testing of an integrated circuit component, it is often desired to be able to evaluate the timing relationship of signals. For example, when testing the propagation delay of a circuit component, it is helpful to be able to compare the timing relationship of an input signal with that of an output signal. Similarly, when testing for race conditions in combinational logic circuits, it is often desired to closely compare the timing of two or more relatively independent signals.
Accordingly, it is desired to provide a system that offers such testing capabilities in connection with a scan-type integrated circuit tester.